What is Oasys-RTL?
Oasys-RTL addresses the needs for greater capacity, reduced runtimes, improved quality of results (QoR), and enhanced physical awareness by conducting optimization at a higher abstraction level while integrating features for floorplanning and placement. By enhancing physical accuracy and streamlining optimization cycles, this tool significantly elevates the quality of the final results, facilitating timely design closure. Its synthesis capabilities are power-aware, featuring support for multi-threshold libraries, automatic clock gating, and a flow based on UPF for multi-voltage domains. Throughout the synthesis phase, Oasys-RTL smartly integrates level shifters, isolation cells, and retention registers as per the power intent defined in the UPF framework. Furthermore, Oasys-RTL boasts the ability to create a floorplan directly from the design's RTL through dataflow application while adhering to various constraints such as timing, power, area, and congestion. It skillfully incorporates regions, fences, blockages, and other physical directives using sophisticated floorplan editing tools, automatically optimizing the layout by positioning macros, pins, and pads. This comprehensive method not only simplifies the management of intricate designs but also ensures that designers can fulfill rigorous performance expectations effectively. Ultimately, Oasys-RTL stands out as a vital tool for modern design challenges, enabling teams to achieve optimal results with efficiency and precision.
Integrations
Screenshots and Video
