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What is JTAG Maps?

JTAG Mapsâ„¢, a user-friendly extension for Altium, enables engineers to efficiently evaluate the testing capabilities offered by JTAG devices integrated into their designs. Previously, engineers dedicated significant time to manually marking boundary-scan nets within a design to assess their coverage. The boundary scan device model files, known as BSDLs, play an essential role in the JTAG and boundary scanning process by specifying which pins can be manipulated through JTAG. JTAG Maps supports BSDL models and includes an option to 'assume scanner covered.' While many users may opt for the Altium coverage report provided by JTAG Maps, there is also an option to import a more comprehensive analysis. Additionally, data can be exported to JTAG ProVision for in-depth evaluation, allowing engineers to gain further insights. Subsequently, a straightforward message file that encompasses complete fault-coverage details can be re-imported into JTAG Maps for visualization and highlighting purposes. This streamlined process significantly reduces the time engineers need to spend on testing assessments.

What is Ansys VeloceRF?

Ansys VeloceRF streamlines the design workflow by drastically reducing the time needed to synthesize and model complex spiral devices and transmission lines. Users can generate geometries for inductors or transformers in seconds, with modeling and analysis completed in just a few minutes. The software is designed to integrate effortlessly with leading EDA platforms, enabling the creation of layouts that are ready for tape-out. With Ansys VeloceRF, engineers can design devices featuring tightly packed components and lines, leading to a more efficient silicon layout. By evaluating the coupling between different inductive devices before delving into detailed layouts, it helps reduce the design footprint and may even do away with the necessity for guard rings. The size of inductors and the crosstalk among them can greatly influence the overall die size, and Ansys VeloceRF facilitates the development of smaller components through the application of optimization criteria and geometry constraints. Additionally, it examines the coupling between multiple inductors to optimize silicon space and boost the performance of inductors within the circuit, ensuring a more effective and efficient design process. This advanced feature not only increases the accuracy of designs but also simplifies the workflow for engineers managing intricate circuit layouts, ultimately leading to faster project completions and improved outcomes.

Media

Media

Integrations Supported

Allegro X Design Platform
Altium Designer
OrCAD X

Integrations Supported

Allegro X Design Platform
Altium Designer
OrCAD X

API Availability

Has API

API Availability

Has API

Pricing Information

Pricing not provided.
Free Trial Offered?
Free Version

Pricing Information

Pricing not provided.
Free Trial Offered?
Free Version

Supported Platforms

SaaS
Android
iPhone
iPad
Windows
Mac
On-Prem
Chromebook
Linux

Supported Platforms

SaaS
Android
iPhone
iPad
Windows
Mac
On-Prem
Chromebook
Linux

Customer Service / Support

Standard Support
24 Hour Support
Web-Based Support

Customer Service / Support

Standard Support
24 Hour Support
Web-Based Support

Training Options

Documentation Hub
Webinars
Online Training
On-Site Training

Training Options

Documentation Hub
Webinars
Online Training
On-Site Training

Company Facts

Organization Name

Altium

Date Founded

1985

Company Location

United States

Company Website

www.altium.com/products/extensions/platform-extensions/jtag-maps/overview

Company Facts

Organization Name

Ansys

Date Founded

1970

Company Location

United States

Company Website

www.ansys.com/products/semiconductors/ansys-velocerf

Categories and Features

PCB Design

3D Visualization
Autorouting
Collaboration Tools
Component Library
Design Rule Check
Differential Pair Routing
Schematic Editor

Categories and Features

PCB Design

3D Visualization
Autorouting
Collaboration Tools
Component Library
Design Rule Check
Differential Pair Routing
Schematic Editor

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