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What is SiLogy?

Our cutting-edge web platform dramatically accelerates the efficiency of chip developers and verification engineers, enabling them to design and troubleshoot at speeds tenfold compared to previous methods. Verilator allows users to effortlessly launch and run thousands of tests at once with a single click. It also simplifies the sharing of test results and waveforms within teams, supports tagging colleagues on specific signals, and provides comprehensive tracking for test and regression failures. By leveraging Verilator to generate Dockerized simulation binaries, we adeptly distribute test runs across our computing cluster, after which we can compile the results and log files, with the ability to rerun any tests that did not yield waveforms. The use of Docker guarantees that test executions remain consistent and reproducible. SiLogy ultimately enhances the productivity of chip developers by significantly reducing the time spent on design and debugging tasks. Before SiLogy was introduced, the primary approach for identifying issues in failing tests involved the tedious process of manually extracting lines from log files, analyzing waveforms on individual computers, or rerunning simulations that could take an excessive amount of time, often lasting several days. Now, our platform empowers engineers to devote more time to innovation instead of being hindered by tedious debugging procedures, resulting in a more dynamic and creative work environment. This shift not only improves individual productivity but also fosters collaboration among teams, leading to more efficient project outcomes.

What is JTAG Maps?

JTAG Mapsâ„¢, a user-friendly extension for Altium, enables engineers to efficiently evaluate the testing capabilities offered by JTAG devices integrated into their designs. Previously, engineers dedicated significant time to manually marking boundary-scan nets within a design to assess their coverage. The boundary scan device model files, known as BSDLs, play an essential role in the JTAG and boundary scanning process by specifying which pins can be manipulated through JTAG. JTAG Maps supports BSDL models and includes an option to 'assume scanner covered.' While many users may opt for the Altium coverage report provided by JTAG Maps, there is also an option to import a more comprehensive analysis. Additionally, data can be exported to JTAG ProVision for in-depth evaluation, allowing engineers to gain further insights. Subsequently, a straightforward message file that encompasses complete fault-coverage details can be re-imported into JTAG Maps for visualization and highlighting purposes. This streamlined process significantly reduces the time engineers need to spend on testing assessments.

Media

Media

Integrations Supported

Docker
GitHub

Integrations Supported

Allegro X Design Platform
OrCAD X

API Availability

API Availability

Pricing Information

Pricing not provided

Pricing Information

Pricing not provided
Free Version

Supported Platforms

SaaS

Supported Platforms

SaaS

Customer Service / Support

Web-Based Support

Customer Service / Support

24 Hour Support

Training Options

Online Training

Training Options

Not specified

Company Facts

Organization Name

SiLogy

Date Founded

2023

Company Location

United States

Company Website

silogy.io

Company Facts

Organization Name

Altium

Date Founded

1985

Company Location

United States

Company Website

www.altium.com/products/extensions/platform-extensions/jtag-maps/overview

Categories and Features

IC Design

Not specified

PCB Design

Not specified

Categories and Features

PCB Design

Not specified

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