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What is Siemens Aprisa?
Designing at advanced process nodes requires a fresh strategy for place-and-route to effectively manage the increasing complexities involved. Aprisa distinguishes itself as a detailed routing-centric physical design platform specifically designed for modern SoCs. Functioning as a holistic RTL2GDSII solution, Aprisa supports digital implementation by offering extensive synthesis and place-and-route features for both top-level hierarchical designs and individual block executions. Its compatibility with signoff tools for STA timing and DRC ensures a high-quality correlation for tape-out, significantly reducing design closure hurdles while maintaining optimal performance, power efficiency, and area enhancement (PPA). Thanks to its impressive out-of-the-box performance, Aprisa empowers physical designers to optimize each step of the place-and-route process, thereby expediting their time-to-market. Furthermore, the integrated architecture and shared analysis engines in Aprisa provide exceptional timing and DRC correlation throughout all implementation phases and with signoff tools, which greatly diminishes the number of flow iterations and engineering change orders (ECOs). Consequently, this progressive methodology not only boosts productivity but also significantly elevates the quality of design in intricate projects. This shift in approach is vital as the semiconductor industry continues to evolve rapidly, demanding even more sophisticated solutions.
What is L-Edit Photonics?
Develop your photonic integrated circuit using a layout-centric workflow that provides designers the flexibility to choose between a drag-and-drop interface and a script-based method. Both options are supported by an extensive custom IC design layout editor, which also oversees the physical verification and tape-out phases. L-Edit Photonics enables swift creation of photonic designs with its user-friendly drag-and-drop feature, which eliminates the necessity for programming. Once the design is complete, a netlist can be generated to facilitate photonic simulations. The integration of the PIC design within the IC layout editor allows users to create layouts without any coding, promoting a layout-focused approach that operates independently of a schematic. For those inclined towards a schematic flow, S-Edit serves as an optional resource. Furthermore, a simulation netlist can be derived for use in a photonic simulator, with photonic simulations being easily integrated through collaborations with various providers. Additionally, numerous foundries supply photonic PDKs to bolster design capabilities. This robust workflow not only simplifies the photonic design process but also accommodates a wide range of designer preferences and methodologies, ensuring that both novice and experienced designers can effectively create and simulate their circuits.
Integrations Supported
Ansys SIwave
Python
API Availability
Has API
API Availability
Has API
Pricing Information
Pricing not provided.
Free Trial Offered?
Free Version
Pricing Information
Pricing not provided.
Free Trial Offered?
Free Version
Supported Platforms
SaaS
Android
iPhone
iPad
Windows
Mac
On-Prem
Chromebook
Linux
Supported Platforms
SaaS
Android
iPhone
iPad
Windows
Mac
On-Prem
Chromebook
Linux
Customer Service / Support
Standard Support
24 Hour Support
Web-Based Support
Customer Service / Support
Standard Support
24 Hour Support
Web-Based Support
Training Options
Documentation Hub
Webinars
Online Training
On-Site Training
Training Options
Documentation Hub
Webinars
Online Training
On-Site Training
Company Facts
Organization Name
Siemens
Date Founded
1847
Company Location
United States
Company Website
eda.sw.siemens.com/en-US/ic/aprisa/
Company Facts
Organization Name
Siemens
Date Founded
1847
Company Location
United States
Company Website
eda.sw.siemens.com/en-US/ic/ic-custom/photonic/l-edit-photonics/