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What is Siemens Solido?

Thousands of designers at top semiconductor companies worldwide rely on Solido's variation-aware design solutions, which encompass IP validation, library characterization, and advanced simulation technologies powered by state-of-the-art AI. This comprehensive suite includes AI-optimized SPICE, Fast SPICE, and mixed-signal simulators that enable clients to accelerate essential design and verification tasks for sophisticated analog, mixed-signal, and custom IC designs significantly. It provides the fastest and most comprehensive integrated IP validation solution in the industry, guaranteeing thorough IP quality assurance from the initial design stage through to tape-out, while addressing all design aspects and incorporating IP updates efficiently. Additionally, this all-encompassing AI-driven design environment supports both nominal and variation-aware verification for custom IC circuits, ensuring complete design coverage with a dramatically reduced number of simulations, all while achieving accuracy on par with traditional brute-force techniques. In addition, it presents swift and accurate library characterization tools that utilize machine learning to boost performance and reliability. By streamlining these processes, designers can focus more on innovation and less on time-consuming verification tasks.

What is Oasys-RTL?

Oasys-RTL addresses the needs for greater capacity, reduced runtimes, improved quality of results (QoR), and enhanced physical awareness by conducting optimization at a higher abstraction level while integrating features for floorplanning and placement. By enhancing physical accuracy and streamlining optimization cycles, this tool significantly elevates the quality of the final results, facilitating timely design closure. Its synthesis capabilities are power-aware, featuring support for multi-threshold libraries, automatic clock gating, and a flow based on UPF for multi-voltage domains. Throughout the synthesis phase, Oasys-RTL smartly integrates level shifters, isolation cells, and retention registers as per the power intent defined in the UPF framework. Furthermore, Oasys-RTL boasts the ability to create a floorplan directly from the design's RTL through dataflow application while adhering to various constraints such as timing, power, area, and congestion. It skillfully incorporates regions, fences, blockages, and other physical directives using sophisticated floorplan editing tools, automatically optimizing the layout by positioning macros, pins, and pads. This comprehensive method not only simplifies the management of intricate designs but also ensures that designers can fulfill rigorous performance expectations effectively. Ultimately, Oasys-RTL stands out as a vital tool for modern design challenges, enabling teams to achieve optimal results with efficiency and precision.

Media

Media

Integrations Supported

Additional information not provided

Integrations Supported

Additional information not provided

API Availability

API Availability

Pricing Information

Pricing not provided

Pricing Information

Pricing not provided

Supported Platforms

Windows
Linux

Supported Platforms

Windows
Linux

Customer Service / Support

Standard Support
Web-Based Support

Customer Service / Support

Standard Support
Web-Based Support

Training Options

Documentation Hub
Webinars
On-Site Training

Training Options

Documentation Hub
Webinars
On-Site Training

Company Facts

Organization Name

Siemens

Date Founded

1847

Company Location

United States

Company Website

eda.sw.siemens.com/en-US/ic/solido/

Company Facts

Organization Name

Siemens

Date Founded

1847

Company Location

United States

Company Website

eda.sw.siemens.com/en-US/ic/oasys-rtl/

Categories and Features

IC Design

Not specified

Categories and Features

IC Design

Not specified

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